1. Field of the Invention
The invention relates generally to image sensor structures. More particularly, the invention relates to image sensor structures with enhanced performance and reliability.
2. Description of the Related Art
Beyond purely electronic microelectronic structures and semiconductor structures such as but not limited to microprocessor structures and memory cell structures, microelectronic structures and semiconductor structures also include optoelectronic structures, such as but not image sensor structures and light emitting diode structures. Image sensor structures are particularly desirable within the context of optoelectronic structures, since image sensor structures find use within various common optoelectronic applications, such as digital cameras.
While image sensor structures are thus desirable within the microelectronic structure and semiconductor structure fabrication art, image sensor structures are nonetheless not entirely without problems. In particular image sensor structures are often fabricated using multiple material layers that may be incompatible, and that may need to conform to both optical and electrical requirements when fabricating an image sensor structure. For that reason, image sensor structures are often susceptible to enhanced cracking, delamination and related failures that may otherwise compromise reliability and functionality of a particular image sensor structure.
Various semiconductor structures having desirable properties, within the context of delamination inhibition, crack inhibition or related quality or reliability considerations, and methods for fabricating those semiconductor structures, are generally known in the semiconductor fabrication art.
Particular disclosures include: (1) Dinkel et al., in U.S. Pat. No. 5,834,829 (which teaches a crack stop structure that includes at least one metallization layer that surrounds an active region within a semiconductor substrate); (2) Cook, in U.S. Pat. No. 6,174,814 (a crack stop structure that channels a crack within a horizontal direction rather than a vertical direction within a laminated dielectric layer stack; (3) Werking, in U.S. Pat. No. 6,709,954 (a scribe seal structure that includes crack stop properties); (4) Agarwala et al., in U.S. Pat. No. 6,734,090 and U.S. Pat. No. 7,163,883 (an edge seal structure that provides crack stop properties with respect to a low dielectric constant dielectric material); (5) Kellar et al., in U.S. Pat. No. 7,056,807 (an edge barrier structure for use within a multiple wafer bonded vertical stack); (6) Fitzsimmons et al. in U.S. Pat. No. 7,109,093 (a crack stop layer that includes a release liner); and (7) Watanabe et al., in U.S. Pat. No. 7,129,565 (a semiconductor structure that includes a crack stop sub-wall portion).
Similarly, and more specifically, various image sensor structures having desirable properties, within the context of delamination inhibition, crack inhibition or related quality or reliability considerations, and methods for fabricating those image sensor structures, are more specifically also known in the image sensor fabrication art.
Particular examples include: (1) Kim, in Korean Patent Publication No. KR 20040095971 and KR 20040095973 (a laminated and offset passivation layer for crack inhibition within a pad region within an image sensor); (2) Park, in Korean Patent Publication Number KR 2004006748 (a CMOS image sensor that includes a dummy edge die region); and (3) Oh et al., in “Enhancement of Wafer Test/Package Yields by Oxide-Capping of Microlens in CMOS Image Sensor,” Proceedings of The Second IEEE Asia Pacific Conference on ASICs. Aug. 28-30, 2000, IEEE 2000, 0-7803-6470-8/00 (general methods for fabricating image sensor structures).
Crack inhibition and delamination inhibition within semiconductor structures, and more particularly within image sensor structures, is likely to be of considerable continued importance as semiconductor structure fabrication technology, and in particular image sensor fabrication technology, advances. To that end, desirable are image sensor structures and methods for fabrication thereof, with inhibited delamination, cracking and related quality and reliability failures.